/*******************************************************************
 * Copyright (C) 2010-2020 Xilinx, Inc. All rights reserved.*
 * SPDX-License-Identifier: MIT
*******************************************************************************/

#include "xparameters.h"
#include "xdphy.h"

/*
* The configuration table for devices
*/

XDphy_Config XDphy_ConfigTable[] =
{
	{
		XPAR_MIPI_DPHY_0_DEVICE_ID,
		XPAR_MIPI_DPHY_0_BASEADDR,
		XPAR_MIPI_DPHY_0_DPHY_MODE,
		XPAR_MIPI_DPHY_0_EN_REG_IF,
		XPAR_MIPI_DPHY_0_DPHY_LANES,
		XPAR_MIPI_DPHY_0_ESC_CLK_PERIOD,
		XPAR_MIPI_DPHY_0_ESC_TIMEOUT,
		XPAR_MIPI_DPHY_0_HS_LINE_RATE,
		XPAR_MIPI_DPHY_0_HS_TIMEOUT,
		XPAR_MIPI_DPHY_0_LPX_PERIOD,
		XPAR_MIPI_DPHY_0_STABLE_CLK_PERIOD,
		XPAR_MIPI_DPHY_0_TXPLL_CLKIN_PERIOD,
		XPAR_MIPI_DPHY_0_WAKEUP,
		XPAR_MIPI_DPHY_0_EN_TIMEOUT_REGS,
		XPAR_MIPI_DPHY_0_HS_SETTLE_NS
	},
	{
		XPAR_MIPI_CSI2_RX_SUBSYSTEM_0_MIPI_DPHY_0_DEVICE_ID,
		XPAR_MIPI_CSI2_RX_SUBSYSTEM_0_MIPI_DPHY_0_BASEADDR,
		XPAR_MIPI_CSI2_RX_SUBSYSTEM_0_MIPI_DPHY_0_DPHY_MODE,
		XPAR_MIPI_CSI2_RX_SUBSYSTEM_0_MIPI_DPHY_0_EN_REG_IF,
		XPAR_MIPI_CSI2_RX_SUBSYSTEM_0_MIPI_DPHY_0_DPHY_LANES,
		XPAR_MIPI_CSI2_RX_SUBSYSTEM_0_MIPI_DPHY_0_ESC_CLK_PERIOD,
		XPAR_MIPI_CSI2_RX_SUBSYSTEM_0_MIPI_DPHY_0_ESC_TIMEOUT,
		XPAR_MIPI_CSI2_RX_SUBSYSTEM_0_MIPI_DPHY_0_HS_LINE_RATE,
		XPAR_MIPI_CSI2_RX_SUBSYSTEM_0_MIPI_DPHY_0_HS_TIMEOUT,
		XPAR_MIPI_CSI2_RX_SUBSYSTEM_0_MIPI_DPHY_0_LPX_PERIOD,
		XPAR_MIPI_CSI2_RX_SUBSYSTEM_0_MIPI_DPHY_0_STABLE_CLK_PERIOD,
		XPAR_MIPI_CSI2_RX_SUBSYSTEM_0_MIPI_DPHY_0_TXPLL_CLKIN_PERIOD,
		XPAR_MIPI_CSI2_RX_SUBSYSTEM_0_MIPI_DPHY_0_WAKEUP,
		XPAR_MIPI_CSI2_RX_SUBSYSTEM_0_MIPI_DPHY_0_EN_TIMEOUT_REGS,
		XPAR_MIPI_CSI2_RX_SUBSYSTEM_0_MIPI_DPHY_0_HS_SETTLE_NS
	}
};
